View AD7693BRMZ_6531424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16-bit, 0.5 lsb, 500 ksps pulsar ? differential adc in msop/qfn ad7693 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2011 analog devices, inc. all rights reserved. features 16-bit resolution with no missing codes throughput: 500 ksps inl/dnl: 0.25 lsb typ, 0.5 lsb max (8 ppm of fsr) dynamic range: 96.5 db sinad: 96 db @ 1 khz thd: ?120 db @ 1 khz true differential analog input range: v ref 0 v to v ref with v ref up to vdd on both inputs no pipeline delay single-supply 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi?/qspi?/microwire?/dsp compatible daisy-chain multiple adcs, selectable busy indicator power dissipation: 40 nj/conversion 40 w @ 5 v/1 ksps 4 mw @ 5 v/100 ksps 18 mw @ 5 v/500 ksps standby current: 1 na 10-lead package: msop (msop-8 size) and 3 mm 3 mm qfn (lfcsp) (sot-23 size) pin-for-pin compatible with the 16-bit ad7687 and ad7688 and the 18-bit ad7690 and ad7691 applications battery-powered equipment data acquisitions seismic data acquisition systems dvms instrumentation medical instruments 1.0 ?1.0 0 65536 code inl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 16384 32768 49152 positive inl = +0.17lsb negative inl = ?0.17lsb 06394-001 figure 1. integral nonlinearity vs. code application diagram ad7693 ref gnd vdd in+ in? vio sdi sck sdo cnv +1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) +2.5v to +5v 10v, 5v, ... +5 v ada4941-1 0 6394-002 figure 2. table 1. msop, qfn (lfcsp)/sot-23 14-/16-/18-bit pulsar adc type 100 ksps 250 ksps 400 ksps to 500 ksps adc driver 18-bit ad7691 ad7690 ada4941-1 ada4841-x 16-bit true differential ad7684 ad7687 ad7688 ad7693 ada4941-1 ada4841-x 16-bit pseudo ad7683 ad7685 ad7686 ada4841-x differential/ unipolar ad7680 ad7694 14-bit ad7940 ad7942 ad7946 ada4841-x general description the ad7693 is a 16-bit, successive approximation analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 16-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. the reference voltage, v ref , is applied externally and can be set up to the supply voltage, vdd. on the cnv rising edge, it samples the voltage difference between the in+ and in? pins. the voltages on these pins swing in opposite phase between 0 v and v ref about v ref /2. its power scales linearly with throughput. using the sdi input, the spi-compatible serial interface also features the ability to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio supply. the ad7693 is housed in a 10-lead msop or a 10-lead qfn (lfcsp) with operation specified from ?40c to +85c.
ad7693 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 application diagram........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications....................................................................... 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configurations and function descriptions ........................... 7 terminology ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 circuit information.................................................................... 12 converter operation.................................................................. 12 typical connecti on diagram ................................................... 13 analog inputs.............................................................................. 14 driver amplifier choice ........................................................... 14 single-ended-to-differential driver ....................................... 15 voltage reference input ............................................................ 15 power supply............................................................................... 15 supplying the adc from the reference.................................. 16 digital interface.......................................................................... 16 cs mode, 3-wire without busy indicator ............................. 17 cs mode, 3-wire with busy indicator .................................... 18 cs mode, 4-wire without busy indicator ............................. 19 cs mode, 4-wire with busy indicator .................................... 20 chain mode without busy indicator ...................................... 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating ad7693 performance............................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 6/11rev. 0 to rev. a changes to resolution parameter and common-mode input range parameter in table 2............................................................. 3 changes to figure 6 and table 6..................................................... 7 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 12/06revision 0: initial version
ad7693 rev. a | page 3 of 24 specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 16 bits analog input voltage range in+ ? (in?) ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? v ref /2 C 0.1 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 65 db leakage current at 25c acquisition phase 1 na input impedance 1 throughput conversion rate 0 500 ksps transient response full-scale step 400 ns accuracy no missing codes 16 bits integral linearity error ?0.5 0.25 +0.5 lsb 2 differential linearity error ?0.5 0.25 +0.5 lsb transition noise ref = vdd = 5 v 0.35 lsb gain error 3 ?20 0.5 +20 lsb gain error temperature drift 0.3 ppm/c zero error 3 ?5 0.5 +5 lsb zero temperature drift 0.3 ppm/c power supply sensitivity vdd = 5 v 5% 1 ppm ac accuracy 4 dynamic range 96 96.5 db 5 signal-to-noise f in = 1 khz 95.5 96 db f in = 10 khz 95.5 db f in = 100 khz 93 db f in = 1 khz, v ref = 2.5 v 93 db signal-to-(noise + distortion) f in = 1 khz 95.5 96 db f in = 10 khz 95.5 db f in = 100 khz 90 db total harmonic distortion f in = 1 khz ?120 ?108 db f in = 10 khz ?113 db f in = 100 khz ?92 db spurious-free dynamic range f in = 1 khz 120 db f in = 10 khz 114 db f in = 100 khz 93.5 db intermodulation distortion 6 115 db 1 see the analog inputs section. 2 lsb means least significant bit. with the 5 v input range, one lsb is 152.6 v. 3 see the terminology section. these specif ications include full temperature range variation but not the error contribution from the external reference. 4 with v ref = 5 v, unless otherwise noted. 5 all specifications expressed in decibels are referred to a full-scale input fsr and tested with an input signal at 0.5 db belo w full scale, unless otherwise specified. 6 f in1 = 21.4 khz and f in2 = 18.9 khz, with each tone at ?7 db below full scale.
ad7693 rev. a | page 4 of 24 vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3. parameter conditions/comments min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 500 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5v 2.5 ns digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 16 bits, twos complement pipeline delay 1 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4. 5 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 2 , 3 vdd and vio = 5 v, 25c 1 50 na power dissipation 100 sps throughput 5 w 100 ksps throughput 4 mw 500 ksps throughput 18 21.5 mw energy per conversion 40 nj temperature range 4 specified performance t min to t max ?40 +85 c 1 conversion results available immediately after completed conversion. 2 with all digital inputs forced to vio or gnd as required. 3 during acquisition phase. 4 contact an analog devices sales representative for the extended temperature range.
ad7693 rev. a | page 5 of 24 timing specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 4. 1 parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2.0 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 4 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 10 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 4 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns 1 see figure 3 and figure 4 for load conditions.
ad7693 rev. a | page 6 of 24 absolute maximum ratings table 5. parameter rating analog inputs in+, 1 in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance (msop-10) 200c/w jc thermal impedance (msop-10) 44c/w lead temperature range jedec j-std-20 1 see the analog inputs section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 500a i ol 500a i oh 1.4v t o sdo c l 50pf 0 6394-003 figure 3. load circuit fo r digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t delay 12v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 20.8v if vio above 2.5v, 0.5v if vio below 2.5v. 06394-004 figure 4. voltage levels for timing
ad7693 rev. a | page 7 of 24 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7693 top view (not to scale) 06394-005 figure 5. 10-lead msop pin configuration 1 ref 2 vdd 3 in+ 4 in? 5 g nd notes 1. the exposed pad is connected to gnd. this connection is not required to meet the electrical performances. 10 vio 9sdi 8sck 7sdo 6cnv top view (not to scale) ad7693 05793-006 figure 6. 10-lead qfn (lfcsp) pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd. it is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part: chain or cs mode. in chain mode, the data should be read when cnv is high. in cs mode, the sdo pin is enabled when cnv is low. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is select ed, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck cycles. cs mode is selected if sdi is high during the cn v rising edge. in this mode, either sdi or cnv can enable the serial output signals when low and if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). epad exposed pad. the exposed pad is connected to gn d. this connection is not required to meet the electrical performances. the exposed pa d is only on the 10-lead qfn (lfcsp). 1 ai = analog input, di = digital input, do = digital output, and p = power.
ad7693 rev. a | page 8 of 24 terminology least significant bit (lsb) the lsb is the smallest increment that can be represented by a converter. for a differential analog-to-digital converter with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 2 (v) = integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 26 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) should occur at a level ? lsb above nominal negative full scale (?4.999847 v for the 5 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999771 v for the 5 v range.) the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits.
ad7693 rev. a | page 9 of 24 typical performance characteristics vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, v ref = vdd, t a = 25c. 1.0 ?1.0 0 65536 code inl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 16384 32768 49152 positive inl = +0.17lsb negative inl = ?0.17lsb 06394-007 figure 7. integral nonlinearity vs. code 300000 0 67 code in hex counts 250000 200000 150000 100000 50000 8 9 abc 00 00 258774 1905 441 0 6394-008 figure 8. histogram of a dc input at the code center 0 ?180 02 frequency (khz) amplitude (db of full scale) 0 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 40 60 20 160 140 120 100 80 180 f s = 500ksps f in = 0.95khz snr = 96.4db thd = ?121db sfdr = 124db sinad = 96.4db 06394-009 figure 9. fft plot 1.0 ?1.0 0 65536 code dnl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 16384 32768 49152 positive dnl = +0.22lsb negative dnl = ?0.22lsb 06394-010 figure 10. differential nonlinearity vs. code 160000 0 7 code in hex counts 120000 140000 100000 80000 60000 40000 20000 89abcd 00 0 126066 135054 00 0 6394-011 figure 11. histogram of a dc input at the code transition snr (db) thd (db) input level (db) ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 snr thd 90 91 92 93 94 95 96 97 98 99 100 ?10 ?8 ?6 ?4 ?2 0 0 6394-012 figure 12. snr, thd vs. input level
ad7693 rev. a | page 10 of 24 snr, sinad (db) enob (bits) reference voltage (v) 90 91 92 93 94 95 96 97 98 99 100 2.0 2.53.03.54.04.5 5.0 5.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 enob 06394-013 snr, sinad figure 13. snr, sinad, and enob vs. reference voltage snr, sinad (db) enob (bits) temperature (c) 90 91 92 93 94 95 96 97 98 99 100 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 ?55 ?35 ?15 5 25 45 65 85 105 125 enob snr, sinad 06394-014 figure 14. snr, sinad, and enob vs. temperature snr, sinad (db) frequency (khz) 0 50 100 150 200 80 82 84 86 88 90 92 94 96 98 100 v in = ?10dbfs v in = ?1dbfs 06394-015 figure 15. sinad vs. frequency thd (db) sfdr (db) reference voltage (v) 80 85 90 95 100 105 110 115 120 125 130 2.0 5.5 sfdr thd ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 06394-016 2.53.03.54.04.55.0 figure 16. thd, sfdr vs. reference voltage thd (db) sfdr (db) temperature (c) ?130 ?125 ?120 ?115 ?110 ?105 ? 100 ?55 ?35 ?15 5 25 45 65 85 105 125 100 105 110 115 120 125 130 sfdr thd v dd = 5v 06394-017 figure 17. thd, sfdr vs. temperature thd (db) frequency (khz) ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 0 50 100 150 200 v in = ?10dbfs v in = ?1dbfs 06394-018 figure 18. thd vs. frequency
ad7693 rev. a | page 11 of 24 operating current (a) supply (v) 0 200 400 600 800 1000 4.50 4.75 5.00 5.25 vdd vio 5.50 06394-019 f s = 100ksps figure 19. operating currents vs. supply operating current (a) temperature (c) 0 200 400 600 800 1000 vdd vio ?55 ?35 ?15 ?5 25 45 65 85 105 125 f s = 100ksps 06394-020 figure 20. operating currents vs. temperature operating current (a) sampling rate (sps) 0.01 10k 1k 100 10 1 0.1 10 1m 100k 10k 1k 100 vdd vio 06394-021 figure 21. operating currents vs. sample rate power-down current (na) temperature (c) 0 1000 800 600 400 200 ?55 12510585654525 5 ?15?35 vdd + vio 06394-022 figure 22. power-down currents vs. temperature temperature (c) zero, gain error (lsb) ?1.0 ?0.5 0 0.5 1.0 ?55 ?35 ?15 5 25 45 65 85 105 125 gain error zero error 06394-023 figure 23. zero error and gain error vs. temperature sdo capacitive load (pf) 120 0 20406080100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c 0 6394-031 figure 24. t dsdo delay vs. capacitance load and supply
ad7693 rev. a | page 12 of 24 theory of operation sw+ msb 16,384c in + lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 32,768c sw? msb 16,384c lsb 4c 2c c c 32,768c 0 6394-024 figure 25. adc simplified schematic circuit information the ad7693 is a fast, low power, single-supply, precise, 16-bit adc using a successive approximation architecture. the ad7693 is capable of converting 500,000 samples per second (500 ksps) and powers down between conversions. when operating at 1 ksps, for example, it consumes 40 w typically, ideal for battery-powered applications. the ad7693 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7693 is specified from 4.5 v to 5.5 v and can be interfaced to any 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-le ad qfn (lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 16-bit ad7687 and ad7688 and with the 18-bit ad7690 and ad7691 . converter operation the ad7693 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in+ and in? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /32,768). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the ad7693 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
ad7693 rev. a | page 13 of 24 transfer functions the ideal transfer characteristic for the ad7693 is shown in figure 26 and table 7 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 0 6394-025 figure 26. adc ideal transfer function table 7. output codes and ideal input voltages description analog input v ref 5 v digital output code (he) fsr ? 1 lsb +4.999847 v 0x7fff 1 midscale + 1 lsb +152.6 v 0x0001 midscale 0 v 0x0000 midscale ? 1 lsb ?152.6 v 0xffff ?fsr + 1 lsb ?4.999847 v 0x8001 ?fsr ?5 v 0x8000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). tpical connection diagram figure 27 shows an example of the recommended connection diagram for the ad7693 when multiple supplies are available. ad7693 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface 5 100nf 100nf 5v 10f 2 v+ v+ v? 1.8v to vdd ref 1 0to v ref 2.7nf 4 v+ v? v ref to 0 2.7nf ada4841-2 3 ada4841-2 3 4 1 see reference section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). 3 see table 8 for additional recommended amplifiers. 4 optional filter. see analog input section. 5 see the digital interface section for most convenient interface mode. 33 ? 33 ? 0 6394-026 figure 27. typical application diagram with multiple supplies
ad7693 rev. a | page 14 of 24 analog inputs figure 28 shows an equivalent circuit of the input structure of the ad7693. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward biased and to start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in? gnd v dd 06394-027 figure 28. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 frequency (khz) cmrr (db) vref = 5v 06394-028 figure 29. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ and in?) can be modeled as a parallel combination of the capacitor, c pin , and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component made up of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7693 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ? 80 0 102030405060708090 33? 50? 100? 0 6394-047 frequency (khz) thd (db) 250 ? vdd = 5v figure 30. thd vs. analog input frequency and source resistance d river amplifier choice although the ad7693 is easy to drive, the driver amplifier must meet the following requirements: x the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7693. the noise coming from the driver is filtered by the ad7693 analog input circuits 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7693 is 56 v rms, the snr degradation due to the amplifier is 2 db3 2 db3 2 )( 2 where: f ?3 db is the input bandwidth in megahertz of the ad7693 (9 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. x for ac applications, the driver should have a thd performance commensurate with the ad7693. x for multichannel multiplexed applications, the driver amplifier and the ad7693 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
ad7693 rev. a | page 15 of 24 table 8. recommended driver amplifiers amplifier typical application ada4941-1 very low noise, low power single to differential ada4841-x very low noise, small, and low power ad8655 5 v single supply, low noise ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single supply, low power single-ended-to-differential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941-1 single-ended-to-differential driver allows for a differential input into the part. the schematic is shown in figure 31 . r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode should be set close to v ref /2; however, if single supply is desired, it can be set slightly above v ref /2 to provide some headroom for the ada4941-1 output stage. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. ad7693 ref gnd vdd in+ 2.7nf 100nf 2.7nf in? +5v ref 10v, 5v, ... +5.2v +5.2v 33 ? 10f r2 c f ada4941 r1 r3 100nf r5 r4 r6 33 ? 06394-029 figure 31. single-ended-to- differential driver circuit voltage reference input the ad7693 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using low temperature drift adr43x and adr44x references. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7693 uses two power supply pins: a core supply, vdd, and a digital input/output interface supply, vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd pins can be tied together. the ad7693 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 32 . 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 frequency (khz) psrr (db) 06394-030 vref = 5v figure 32. psrr vs. frequency the ad7693 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate (refer to figure 21 ). this makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications.
ad7693 rev. a | page 16 of 24 s upplying the adc from the reference for simplified applications, the ad7693, with its low operating current, can be supplied directly using the reference circuit shown in figure 33 . the reference line can be driven by ? the system power supply directly ? a reference voltage with enough current output capability, such as the adr43x ? a reference buffer, such as the ad8031 , which can also filter the system power supply, as shown in figure 33 . ad8031 ad7693 vio ref vdd 10f 1f 10 ? 10k ? 5v 5v 5v 1f 1 1 optional reference buffer and filter. 06394-032 figure 33. example of an application circuit digital interface generally, a user is interested in either minimizing the wiring complexity of a multichannel adc system or communicating with the parts via a specific interface standard. although the adc has only four digital pins (cnv, sck, sdi, and sdo), it offers a significantly flexible serial interface, including compatibility with spi, qspi, digital hosts, and dsps (such as black fin ? adsp-bf53x or adsp-219x ). by configuring the adc into one of six modes, virtually any serial interface scenario can be accommodated. for wiring efficiency, the best way to configure a multichannel, simultaneous-sampling system is to use the 3-wire chain mode. this system is easily created by cascading multiple (m) adcs into a shift register structure. the cnv and clk pins are common to all adcs, and the sdo of one part feeds the sdi of the next part in the chain. the 3-wire interface is simply the cnv, sck, and sdo of the last adc in the chain. for a system containing m- and n-bit converters, the user needs to provide m n sck transitions to read back all of the data. this 3-wire interface is also ideally suited for isolated applications. additional flexibility is provided by optionally configuring the adcs to provide a busy indication. without a busy indication, the user must externally timeout the maximum adc conversion time before commencing readback. this configuration is described in the chain mode without busy indicator section. with the busy indication enabled, external timer circuits are not required because the sdo at the end of the chain provides a low-to-high transition (that is, a start bit) when all of the chain members have completed their conversions and are ready to transmit data. however, one additional sck is required to flush the sdo busy indication prior to reading back the data. this configuration is described in the chain mode with busy indicator section. the primary limitations of 3-wire chain mode are that all adcs are simultaneously sampled and the user cannot randomly select an individual adc for readback. this can be overcome only by increasing the number of wires (for example, one chip select wire per adc). to operate with this increased functionality, the part must be used in cs mode. cs mode is separated into two categories (3-wire and 4-wire) whereby flexibility is traded off for wiring complexity. in cs 4-wire mode, the user has independent control over the sampling operation (via cnv) and the chip select operation (via sdi) for each adc. in cs 3-wire mode, sdi is unused (tied high) and cnv is used to both sample the input and chip select the part when needed. as with chain mode, the parts can optionally be configured to provide a busy indication, but at the expense of one additional sck when reading back the data. so in total there are four cs modes: 3-wire and 4-wire modes, each with busy and without busy. there is no elaborate writing of configuration words into the part via the sdi pin. the mode in which the part operates is defined by ensuring a specific relationship between the cnv, sdi, and sck inputs at key times. to select cs mode, ensure that sdi is high at the rising edge of cnv; otherwise, chain mode will be selected. once in cs mode, selecting the part for readback before the conversion is complete (by bringing either sdi or cnv low) instructs the part to provide a busy indicator, a high-to-low impedance transition on sdo, to tell the user when the conversion has finished. if the part is selected after the conversion has finished, sdo outputs the msb when it is selected. in chain mode, the busy indicator, a low-to-high transition on sdo, is selected based on the state of sck at the rising edge of cnv. if sck is high, the busy indicator is enabled; otherwise, the busy indicator is not enabled. the following sections provide specifics for each of the different serial interface modes. note that in the following sections, the timing diagrams indicate digital activity (sck, cnv) during conversion. however, due to the possibility of performance degradation, digital activity should only occur during the first quarter of the conversion phase because the ad7693 provides error correction circuitry that can correct for an incorrect bit during this time. the user should initiate the busy indicator if desired during this time. it is also possible to corrupt the sample by having sck or sdi transitions near the sampling instant. therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns after the rising edge of cnv. the exception is when the device is in the chain mode with busy configuration, where sdi is tied to cnv, because this scenario does not yield a corrupted sample. to this extent, it is recommended, to use a discontinuous sck whenever possible to avoid any potential performance degradation.
ad7693 rev. a | page 17 of 24 cs mode, 3-wire without busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host. the connection diagram is shown in figure 34 , and the corresponding timing is given in figure 35 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this could be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7693 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. cnv sck sdo sdi data in clk convert v io ad7693 06394-033 digital host figure 34. cs mode, 3-wire without busy indicator connection diagram (sdi high) sdo d15 d14 d13 d1 d0 t dis sck 123 141516 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 06394-034 figure 35. cs mode, 3-wire without busy indicator serial interface timing (sdi high)
ad7693 rev. a | page 18 of 24 cs mode, 3-wire with busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 36 , and the corresponding timing is given in figure 37 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by th e digital host. the ad7693 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad7693s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio cnv sck sdo sdi v io ad7693 0 6394-035 digital host figure 36. cs mode, 3-wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 123 151617 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq 0 6394-036 figure 37. cs mode, 3-wire with busy indicator serial interface timing (sdi high)
ad7693 rev. a | page 19 of 24 cs mode, 4-wire without busy indicator this mode is usually used when multiple ad7693s are connected to an spi-compatible digital host. a connection diagram example using two ad7693s is shown in figure 38 , and the corresponding timing is given in figure 39 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7693 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the 16 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad7693 can be read. data in clk cs1 convert cs2 cnv sck sdo sdi cnv sck sdo sdi ad7693 ad7693 0 6394-037 digital host figure 38. cs mode, 4-wire without busy indicator connection diagram sdo d15 d14 d13 d1 d0 t dis sck 123 303132 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 14 15 t sck t sckl t sckh d0 d16 d15 17 18 16 sdi(cs2) 0 6394-038 figure 39. cs mode, 4-wire without busy indicator serial interface timing
ad7693 rev. a | page 20 of 24 cs mode, 4-wire with busy indicator this mode is usually used when a single ad7693 is connected to an spi-compatible digital host with an interrupt input and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 40 , and the corresponding timing is given in figure 41 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7693 then enters the acquisition phase and powers down. the data bits are clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate, provided it has an acceptable hold time. after the optional 17 th sck falling edge, or when sdi goes high (whichever occurs first), sdo returns to high impedance. data in irq clk convert cs1 vio cnv sck sdo sdi ad7693 06394-039 digital host figure 40. cs mode, 4-wire with busy indicator connection diagram sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 06394-040 figure 41. cs mode, 4-wire with busy indicator serial interface timing
ad7693 rev. a | page 21 of 24 chain mode without busy indicator this mode can be used to daisy-chain multiple ad7693s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7693s is shown in figure 42 , and the corresponding timing is given in figure 43 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7693 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate and consequently more ad7693s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate can be reduced due to the total readback time. clk convert data in cnv sck sdo sdi cnv sck sdo sdi ad7693 b ad7693 a 0 6394-041 digital host figure 42. chain mode without busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 06394-042 figure 43. chain mode without busy indicator serial interface timing
ad7693 rev. a | page 22 of 24 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7693s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7693s is shown in figure 44 , and the corresponding timing is given in figure 45 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7693 adc labeled c in figure 44 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7693 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7693s in the chain, provided the digital host has an acceptable hold time. clk convert data in irq digital host cnv sck sdo sdi cnv sck sdo sdi cnv sck sdo sdi ad7693 b ad7693 c ad7693 a 06394-043 figure 44. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 123 35 47 48 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 415 t sck t sckh t sckl d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1d b 0d a 15 d a 14 49 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1d a 0 d c 1d c 0d a 14 19 31 32 18 33 d b 1d b 0d a 15 d b 15 d b 14 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 06394-044 figure 45. chain mode with busy indicator serial interface timing
ad7693 rev. a | page 23 of 24 application hints layout the printed circuit board that houses the ad7693 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7693, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the ad7693 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7693s. the ad7693 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7693 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7693 and connected using short, wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of a layout following these rules is shown in figure 46 and figure 47 . evaluating ad7693 performance other recommended layouts for the ad7693 are outlined in the documentation of the evaluation board for the ad7693 ( eval-ad7693cb ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3. 06394-045 figure 46. example layout of the ad7693 (top layer) 0 6394-046 figure 47. example layout of the ad7693 (bottom layer)
ad7693 rev. a | page 24 of 24 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 48.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 49. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 notes temperature range package description package option branding ordering quantity ad7693bcpzrl ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 c4y reel, 5,000 ad7693bcpzrl7 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 c4y reel, 1,500 AD7693BRMZ ?40c to +85c 10-lead msop rm-10 c4y tube, 50 AD7693BRMZrl7 ?40c to +85c 10- lead msop rm-10 c4y reel, 1,000 eval-ad7693cbz 2 evaluation board eval-control brd2 3 controller board eval-control brd3 3 controller board 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brdx for evaluation/demonstrat ion purposes. 3 these boards allow a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. ?2006C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05793-0-6/11(a)

▲Up To Search▲

Price & Availability of AD7693BRMZ

	To Download AD7693BRMZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .